Testing and evaluation of digital integrated circuits generally requires the availability of a set of identical digital input waveforms mutually offset in phase. The requisite set of input waveforms may be produced by, for example, phase-locking a delay generator circuit to a reference clock signal. A plurality of phase-shifted replicas of the reference clock signal are then provided by at the various output ports of the delay generator. As is well known, delay generators are often realized using some form of a ring oscillator circuit.
Referring to FIG. 1, there is shown a simplified block diagram of a phase locked loop (PLL) operative to lock the frequency and phase of a reference clock signal to a ring oscillator 10. Once the oscillator 10 becomes locked in frequency and phase to the reference clock signal, a constant phase delay will appear between each of the signals available at adjacent ones of the ring oscillator outputs O.sub.i, i=1 to N. Any desired pair of outputs O.sub.i may then coupled to output terminal T.sub.1 and T.sub.2 by a double multiplexer 11. A pair of outputs O.sub.i, rather than merely a single output O.sub.i, is provided in order that an arbitrary one of the terminals T.sub.1 and T.sub.2 serve as a reference terminal. The output terminal T.sub.1 and T.sub.2 will typically be connected to test equipment (not shown) for evaluating integrated circuit performance.
As is indicated by FIG. 1, the signal generated at the N.sup.th ring oscillator output O.sub.N is provided to one input of a phase comparator 12. The phase comparator 12 then produces either a PUMP UP (UP) or PUMP DOWN (DN) error signal based on the relative phase between the oscillator output O.sub.N and the reference clock signal. The UP or DN error signal produced by phase comparator 12 is then integrated by a charge pump circuit 14 configured as a conventional integrator. A low-pass loop filter 16, connected between the charge pump 14 and a tuning port of the ring oscillator 10, is used to remove the high-frequency components from the integrated phase error signal. The oscillation frequency of the oscillator 10 is then forced to the frequency of the reference clock signal in accordance with the resultant control voltage V.sub.c.
Turning now to FIG. 2, the ring oscillator 10 is seen to include a set of N serially-connected buffer inverters 20. As is indicated by FIG. 2, the output port of each buffer inverter 20 defines one of the outputs O.sub.i of the ring oscillator 10. A closed loop is seen to be established within the ring oscillator 10 by connection of the oscillator output O.sub.N to an input of the buffer inverter 20 defining oscillator output O.sub.1. The delay through each buffer inverter 20 is equivalent to the period of the reference signal divided by 2N, and is set by the value of the control voltage V.sub.c. That is, the value of the control voltage V.sub.c determines the delay through each buffer inverter 20 and thereby controls the operating frequency of the ring oscillator 10. The control voltage V.sub.c will reach a constant value once the ring oscillator 10 becomes phase locked to the reference clock signal.
FIGS. 3A and 3B illustratively represent the phase relationship among the oscillator outputs O.sub.i, i=1 to N for the exemplary case of N=5, which exists during steady-state oscillation of the ring oscillator 10. Specifically, FIG. 3A depicts the waveform produced at output O.sub.1 during a single oscillation period of the oscillator 10. The rising transitions in the waveform of FIG. 3A at the beginning and end of the oscillation period are identified by filled circles, and the falling transition midway therebetween is identified using an open circle. Similarly, FIG. 3B illustrates represents the timing of the rising and falling transitions at each of the outputs O.sub.1 -O.sub.5 during the oscillation period described with reference to FIG. 3A. As is indicated by FIG. 3B, the rising transition at output O.sub.1 at the beginning of the oscillation period induces a corresponding falling transition to occur at output O.sub.2 subsequent to a delay of 0.1 oscillation periods. Assuming that both inverting and non-inverting outputs of each buffer inverter 20 are capable of being tapped, a total of ten different output phases uniformly spanning the output period are made available by the ring oscillator 10.
Unfortunately, when the ring oscillator 10 is utilized as a delay generator the delay resolution between successive outputs O.sub.i is limited by the signal delay introduced by a single one of the buffer inverters 20. Additional output phases could be made available during each oscillation period by increasing the number of inverting buffers within the ring oscillator, but such an increase effectively reduces the maximum oscillation frequency. The net result is that the achievable delay resolution remains equivalent to a single buffer delay.
Accordingly, it is an object of the present invention to provide a ring-like oscillator circuit in which the number of buffer inverters may be increased without concomitantly reducing the maximum oscillation frequency. Such a circuit architecture would advantageously allow a delay resolution of less than a buffer delay to be achieved.